Key result
A proposed low-power ECG readout system fabricated in a 0.18-μm CMOS process achieved an input impedance >1 GΩ, input-referred noise of 2.9 μVrms, and consumed 4.5 μA from a 1.2-V supply.
Why the study?
There was a need to design a low-power ECG readout system suitable for recording ECG from dry electrodes while minimizing overall power consumption.
The proposed low-power ECG readout system achieves high input impedance and low power consumption, making it suitable for dry-electrode recording.
May enable dry-electrode ECG monitoring in wearables; leaves open clinical validation.
This paper presents the design of a low-power electrocardiogram (ECG) readout system suitable for use in recording ECG from dry electrodes. To minimize the system's overall power consumption, we employ a very high gain (69 dB) along with a discrete-time signal-folding technique to prevent signal saturation in the amplification stage to reduce the required resolution of the analog-to-digital converter (ADC) to only 8 bits. Fabricated in a standard 0.18- μm CMOS process with an active area of 1.07 mm2, the proposed readout system exhibits an input impedance exceeding 1 G Ω in a bandwidth of 0.5-150 Hz, an overall input-referred noise of 2.9 μVrms, an input range of 12.5 mVpp, while consuming a total current of 4.5 μA from a 1.2-V supply voltage.
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Buaban et al. (2021) studied this question. Low-power ECG readout system with signal-folding technique was evaluated on System performance (input impedance, noise, power consumption). A proposed low-power ECG readout system fabricated in a 0.18-μm CMOS process achieved an input impedance >1 GΩ, input-referred noise of 2.9 μVrms, and consumed 4.5 μA from a 1.2-V supply.
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