A Dual-Channel Readout Low-Noise CMOS Image Sensor Based on Skipper Technology

This is the authors' abstract. We don't add key points for this paper.

With the development of semiconductor fabrication technology, in the 180 nm CMOS image sensor (CIS) process, the gap between two gates has been reduced to0.25~μm. Under this background, charge transfer between gates is realized, like the process in charge-coupled devices (CCDs). In recent literature, skipper technology has been utilized to improve the noise performance of CIS as it was previously applied in CCDs. In this article, a dual-channel readout low-noise CIS based on skipper technology is proposed. Theoretical analysis is introduced to verify the advantages of skipper multiple sampling (SMS), compared with correlated multiple sampling (CMS). Technology computer-aided design (TCAD) simulations were conducted to clarify the relationship between gate voltage level and the charge accommodation capacity and investigate the charge transfer efficiency (CTE) of the proposed pixel. An optimized pipeline readout chain is introduced to eliminate correlated noise and a post-simulation is implemented to study the readout circuit. According to the simulation results, the CTE improvement in the proposed skipper pixel is proved. By means of circuit-level simulations, the linearity of programmable gain amplifier (PGA) and the input-referred noise (IRN) at different gains were obtained. Compared with the conventional skipper structure, the pixel architecture proposed in this article realizes the same noise level with half the number of charge transfers, which mitigates the effect of CTE and improves the frame rate.