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Advanced reliability simulators like Comphy capture much of the state-of-the-art modeling behind charge trapping processes. An alternative approach to Comphy is to apply stochastic models, e.g. the defect-centric model, directly to the experimental data to extract the impact of defects on the device behavior and trap densities. In order to efficiently design defect characterization experiments, however, it is of utmost importance to understand the robustness of the defect-centric model under a variety of pre-conditions. In this work, we evaluate the requirements to employ the defect-centric model for data analysis, using simulated data from Comphy based on a real 400 nm × 180 nm pMOS device. Our results show that the number of devices from wafer-level tests does not suffice for statistical evaluation of RTN analysis. Here, preferably array chips should be used. For BTI studies, both wafer-level and array-chip tests enable us to extract good estimates for defect parameters with little computational effort.
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Loesener et al. (2025) studied this question.
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