Neutron Radiation Induced Soft Error Rates for an Adjacent-ECC Protected SRAM in 28 nm CMOS

We report on measured neutron radiation induced soft error rates (SER) for an academic, full-custom, low-power 75 kb SRAM macro in a commercial 28 nm CMOS process protected with an adjacent-bit error correction circuit (ECC). In low voltage (0.5 V) power saving mode, measurements show an 189x improvement in SER over an unprotected baseline array and a 5x improvement over a traditional single-error-correcting-double-error-detecting (SEC-DED) code using the same number of parity check-bits. Further, simulation results show an over 2x reduction in SER compared to other multi-bit ECCs while using three fewer check-bits. Chip measurement results show that the low voltage retention mode provides a 89.7% reduction in cell leakage current/bit compared to the nominal supply voltage. All radiation measurement data has been collected at the TRIUMF Neutron Irradiation Facility in Vancouver, Canada.