An Analysis of the Modes of Operation of Parasitic SCRs

Four-layer parasitic SCR paths exist in bulk CMOS integrated circuits which can be activated by transient ionizing radiation, by overvoltage stress, and by other means into a low-impedance state (latch-up). These parasitic SCRs often have characteristics which are not explained by simple SCR theory; for example, large holding voltage offsets and saturation of the total current through the device have been observed. This paper analyzes a cross-coupled transistor model to explain how these characteristics can occur in parasitic four-layer paths. Experimental data is presented demonstrating modes of operation present in parasitic SCRs but not normally observed in discrete Shockley diodes or thyristors.