What question did this study set out to answer?

To fabricate and evaluate 1.2 kV normally-off lateral p-GaN high-electron-mobility transistors on large-diameter 200 mm engineered substrates.

February 1, 2024IEEE Electron Device LettersOpen Access

2 kV Enhancement-Mode p-GaN Gate HEMTs on 200 mm Engineered Substrates

View Full Paper

Ask AI

Bookmark

Authors

SKS. KumarIMEC KGKaren GeensIMEC AVAnurag VohraIMEC

Discussion

Member takes

Implication

Experimental study demonstrates 1.2 kV enhancement-mode p-GaN HEMTs on 200 mm engineered substrates, indicating high uniformity and reliability for power electronics.

Key Points

To fabricate and evaluate 1.2 kV normally-off lateral p-GaN high-electron-mobility transistors on large-diameter 200 mm engineered substrates.
Fabricated enhancement-mode p-GaN gate lateral HEMTs on 200 mm engineered substrates using optimized gate-drain spacing.
Characterized electrical parameters across the wafer, including threshold voltage, specific ON-resistance, and hard breakdown voltage.
Conducted on-wafer high-temperature gate bias (HTGB) and reverse-bias stress testing to assess device stability.
Optimized transistors achieved a threshold voltage of 3.2 V, an ON/OFF current ratio of 10⁸, a low specific ON-resistance of 5.8 mΩ·cm², and a hard breakdown voltage of 1800 V.
Devices exhibited high wafer-scale uniformity with an ON-resistance variation (σ_Ron) of 1.2%.
Transistors successfully passed on-wafer HTGB and reverse-bias stress tests with zero recorded device failures.

Cite This Study

Kumar et al. (2024) studied this question.

synapsesocial.com/papers/6aa8518e5d9410427ecdf0d1 https://doi.org/10.1109/led.2024.3361164

View Full Paper

Ask AI

Bookmark

February 1, 2024IEEE Electron Device LettersOpen Access

2 kV Enhancement-Mode p-GaN Gate HEMTs on 200 mm Engineered Substrates

View Full Paper

Ask AI

Bookmark

Authors

SKS. KumarIMEC KGKaren GeensIMEC AVAnurag VohraIMEC

Discussion

Member takes

Implication

Experimental study demonstrates 1.2 kV enhancement-mode p-GaN HEMTs on 200 mm engineered substrates, indicating high uniformity and reliability for power electronics.

Key Points

To fabricate and evaluate 1.2 kV normally-off lateral p-GaN high-electron-mobility transistors on large-diameter 200 mm engineered substrates.
Fabricated enhancement-mode p-GaN gate lateral HEMTs on 200 mm engineered substrates using optimized gate-drain spacing.
Characterized electrical parameters across the wafer, including threshold voltage, specific ON-resistance, and hard breakdown voltage.
Conducted on-wafer high-temperature gate bias (HTGB) and reverse-bias stress testing to assess device stability.
Optimized transistors achieved a threshold voltage of 3.2 V, an ON/OFF current ratio of 10⁸, a low specific ON-resistance of 5.8 mΩ·cm², and a hard breakdown voltage of 1800 V.
Devices exhibited high wafer-scale uniformity with an ON-resistance variation (σ_Ron) of 1.2%.
Transistors successfully passed on-wafer HTGB and reverse-bias stress tests with zero recorded device failures.

Cite This Study

Kumar et al. (2024) studied this question.

synapsesocial.com/papers/6aa8518e5d9410427ecdf0d1 https://doi.org/10.1109/led.2024.3361164

Also Consider

Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context:

View Full Paper

Ask AI

Bookmark