300 Mm sSOI engineering with ultra thin buried oxide

This paper presents the fabrication of 300 mm tensile-strained silicon-on-insulator (sSOI) wafers designed for next-generation fully depleted silicon-on-insulator (FD-SOI) CMOS devices. The wafers feature a 25 nm thick buried oxide (BOX) and a 12 nm thick tensile-strained top silicon layer. The integration scheme involved growing a thin silicon layer on a relaxed SiGe thick graded buffer, followed by partial transfer to a base wafer using the Smart Cut™ process. The tensile stress in the top silicon layer was successfully modulated from 0.6 GPa to 1.8 GPa by adjusting the germanium content in the SiGe thick graded buffer underneath. Transmission electron microscopy and Raman spectroscopy confirmed the high crystalline quality and uniform strain distribution across the wafers. The study demonstrates the potential for achieving different levels of strain to optimize the performance of nMOS devices.