Application of RADSAFE to Model the Single Event Upset Response of a 0.25 μm CMOS SRAM

The RADSAFE simulation framework is described and applied to model SEU in a 0.25 mum CMOS 4 Mbit SRAM. For this circuit, the RADSAFE approach produces trends similar to those expected from classical rectangular parallelepiped models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit.