Single Event Upset (SEU) characteristics of a digital emitter coupled logic (ECL) device clocking at 0.5, 1, and 3.2 GHz and at temperatures of 5, 75, and 105/spl deg/ C are presented. The test technique is explained. Observations of two types of upsets, phase upsets at low Linear Energy Transfer (LETs) and amplitude upsets at high LETs are also presented. The cause of phase upsets is discussed. The effect of each type of upset on the system is discussed. The upset cross section and LET threshold seem to be insensitive to temperatures below 75/spl deg/C and to the clock frequencies tested.>
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Shoga et al. (1994) studied this question.