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The combined effects of TID, process corner, and temperature on the performance of high frequency RF circuits are presented. TID experiments at 25∘ Cand 100∘ Con NMOSFETs and PMOSFETs fabricated in a commercial 45 nm technology show varied degradation in DC and RF performance. The combination of variation due to TID, process, and temperature causes the NMOSFET parameters to fall out of the pre-irradiation process/voltage/temperature (PVT) operating space. TID-aware compact models of MOSFETs are developed based on measured parametric degradation of the transistor behavior. The compact models are used to design a K-band LC voltage-controlled oscillator (VCO), operating at 22 GHz without any compensation circuitry. Circuit simulations show that a 500krad( SiO₂)dose on the VCO operating at 100∘ Cand at the slow process corner can result in circuit failure for biases less than 500 mV. For higher biases, TID causes degradation in frequency, amplitude, and phase noise, causing inability of the VCO to meet the desired performance specifications.
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Jagannathan et al. (2013) studied this question.
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