The total safe operating area (SOA) of LDMOS transistors is discussed. It is shown that the transistors are subjected to different kinds of stresses, yielding a combination of electrical and thermal degradation and/or failure modes. A methodology to build the total SOA for LDMOS transistors is highlighted and is experimentally verified on a 40-V LDMOS implemented in a
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Moens et al. (2006) studied this question.
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